Datasheet Summary
IS61NLP25636A/IS61NVP25636A IS61NLP51218A/IS61NVP51218A
256K x 36 and 512K x 18 9Mb, PIPELINE 'NO WAIT' STATE BUS SRAM
AUGUST 2014
Features
- 100 percent bus utilization
- No wait cycles between Read and Write
- Internal self-timed write cycle
- Individual Byte Write Control
- Single R/W (Read/Write) control pin
- Clock controlled, registered address, data and control
- Interleaved or linear burst sequence control us- ing MODE input
- Three chip enables for simple depth expansion and address pipelining
- Power Down mode
- mon data inputs and data outputs
- CKE pin to enable clock and suspend operation
- JEDEC 100-pin TQFP, 165-ball PBGA and
119-ball PBGA packages
- Power supply:
NVP:...
