IS61NVP51218A - 9Mb STATE BUS SRAM

This page provides the datasheet information for the IS61NVP51218A, a member of the IS61NVP25636A 9Mb STATE BUS SRAM family.

Product Overview

ISSI

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Datasheet Details

Part number	IS61NVP51218A
Manufacturer	ISSI
File Size	681.44 KB
Description	9Mb STATE BUS SRAM
Datasheet	IS61NVP51218A Datasheet
Additional preview pages of the IS61NVP51218A datasheet.

IS61NVP51218A Product details

Description

The 9 Meg 'NLP/NVP' product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, 'no wait' state, device for networking and communications applications.

Features

100 percent bus utilization.
No wait cycles between Read and Write.
Internal self-timed write cycle.
Individual Byte Write Control.
Single R/W (Read/Write) control pin.
Clock controlled, registered address, data and control.
Interleaved or linear burst sequence control us- ing MODE input.
Three chip enables for simple depth expansion and address pipelining.
Power Down mode.
Common data inputs and data outp.

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Other Datasheets by ISSI

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Published: Jul 12, 2008 |