IS61QDPB21M36A2
Description
The and are synchronous, high- performance CMOS static random access memory (SRAM) devices. These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround.
Key Features
- 1Mx36 and 2Mx18 configuration available.
- On-chip Delay-Locked Loop (DLL) for wide data valid window.
- Separate independent read and write ports with concurrent read and write operations.
- Synchronous pipeline read with EARLY write operation.
- Double Data Rate (DDR) interface for read and write input ports.
- 2.5 Cycle read latency.
- Fixed 2-bit burst for read and write operations.
- Clock stop support.
- Two input clocks (K and K#) for address and control registering at rising edges only.
- Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.
