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IS61QDPB22M36C - 72Mb QUADP Synchronous SRAM

Download the IS61QDPB22M36C datasheet PDF. This datasheet also covers the IS61QDPB24M18C variant, as both devices belong to the same 72mb quadp synchronous sram family and are provided as variant models within a single manufacturer datasheet.

General Description

at page 6 for each ODT option.

The IS61QDPB22M36C/C1/C2 and IS61QDPB24M18C/C1/ -C2 are 72Mb synchronous, high-performance CMOS static random access memory (SRAM) devices.

These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround.

Key Features

  • 2Mx36 and 4Mx18 configuration available.
  • On-chip Delay-Locked Loop (DLL) for wide data valid window.
  • Separate independent read and write ports with concurrent read and write operations.
  • Max. 450 MHz clock for high bandwidth.
  • Synchronous pipeline read with EARLY write operation.
  • Double Data Rate (DDR) interface for read and write input ports.
  • 2.5 Cycle read latency.
  • Fixed 2-bit burst for read and write operations.
  • Two input clocks (K and K#) fo.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (IS61QDPB24M18C-ISSI.pdf) that lists specifications for multiple related part numbers.

Full PDF Text Transcription for IS61QDPB22M36C (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for IS61QDPB22M36C. For precise diagrams, and layout, please refer to the original PDF.

IS61QDPB24M18C/C1/C2 IS61QDPB22M36C/C1/C2 4Mx18, 2Mx36 72Mb QUADP (Burst 2) Synchronous SRAM (2.5 CYCLE READ LATENCY) APRIL 2018 FEATURES  2Mx36 and 4Mx18 configuration ...

View more extracted text
CLE READ LATENCY) APRIL 2018 FEATURES  2Mx36 and 4Mx18 configuration available.  On-chip Delay-Locked Loop (DLL) for wide data valid window.  Separate independent read and write ports with concurrent read and write operations.  Max. 450 MHz clock for high bandwidth  Synchronous pipeline read with EARLY write operation.  Double Data Rate (DDR) interface for read and write input ports.  2.5 Cycle read latency.  Fixed 2-bit burst for read and write operations.  Two input clocks (K and K#) for address and control registering at rising edges only.  Two echo clocks (CQ and CQ#) that are delivered simultaneously with da

More Datasheets from ISSI (now Infineon)

Part Number Description
IS61QDPB22M36C1 72Mb QUADP Synchronous SRAM
IS61QDPB22M36C2 72Mb QUADP Synchronous SRAM
IS61QDPB22M36A 72Mb QUADP (Burst 2) Synchronous SRAM
IS61QDPB22M36A1 72Mb QUADP (Burst 2) Synchronous SRAM
IS61QDPB22M36A2 72Mb QUADP (Burst 2) Synchronous SRAM
IS61QDPB22M18A 36Mb QUADP (Burst 2) Synchronous SRAM
IS61QDPB22M18A1 36Mb QUADP (Burst 2) Synchronous SRAM
IS61QDPB22M18A2 36Mb QUADP (Burst 2) Synchronous SRAM
IS61QDPB21M18A 18Mb QUADP (Burst 2) Synchronous SRAM
IS61QDPB21M18A1 18Mb QUADP (Burst 2) Synchronous SRAM