Datasheet4U Logo Datasheet4U.com

IS61QDPB24M18C - 72Mb QUADP Synchronous SRAM

General Description

at page 6 for each ODT option.

The IS61QDPB22M36C/C1/C2 and IS61QDPB24M18C/C1/ -C2 are 72Mb synchronous, high-performance CMOS static random access memory (SRAM) devices.

These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround.

Key Features

  • 2Mx36 and 4Mx18 configuration available.
  • On-chip Delay-Locked Loop (DLL) for wide data valid window.
  • Separate independent read and write ports with concurrent read and write operations.
  • Max. 450 MHz clock for high bandwidth.
  • Synchronous pipeline read with EARLY write operation.
  • Double Data Rate (DDR) interface for read and write input ports.
  • 2.5 Cycle read latency.
  • Fixed 2-bit burst for read and write operations.
  • Two input clocks (K and K#) fo.

📥 Download Datasheet

Full PDF Text Transcription for IS61QDPB24M18C (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for IS61QDPB24M18C. For precise diagrams, and layout, please refer to the original PDF.

IS61QDPB24M18C/C1/C2 IS61QDPB22M36C/C1/C2 4Mx18, 2Mx36 72Mb QUADP (Burst 2) Synchronous SRAM (2.5 CYCLE READ LATENCY) APRIL 2018 FEATURES  2Mx36 and 4Mx18 configuration ...

View more extracted text
CLE READ LATENCY) APRIL 2018 FEATURES  2Mx36 and 4Mx18 configuration available.  On-chip Delay-Locked Loop (DLL) for wide data valid window.  Separate independent read and write ports with concurrent read and write operations.  Max. 450 MHz clock for high bandwidth  Synchronous pipeline read with EARLY write operation.  Double Data Rate (DDR) interface for read and write input ports.  2.5 Cycle read latency.  Fixed 2-bit burst for read and write operations.  Two input clocks (K and K#) for address and control registering at rising edges only.  Two echo clocks (CQ and CQ#) that are delivered simultaneously with da