IS61QDPB42M18A Overview
1Mx36 and 2Mx18 configuration available. On-chip Delay-Locked Loop (DLL) for wide data valid window. Separate independent read and write ports with concurrent read and write operations.
IS61QDPB42M18A Key Features
- 1Mx36 and 2Mx18 configuration available
- On-chip Delay-Locked Loop (DLL) for wide data valid window
- Separate independent read and write ports with concurrent read and write operations
- Synchronous pipeline read with late write operation
- Double Data Rate (DDR) interface for read and write input ports
- 2.5 cycle read latency
- Fixed 4-bit burst for read and write operations
- Clock stop support
- Two input clocks (K and K#) for address and control registering at rising edges only
- Two echo clocks (CQ and CQ#) that are delivered simultaneously with data