Datasheet Summary
IS61(4)LPS12836EC/IS61(4)VPS12836EC/IS61(4)LPS12832EC IS61(4)VPS12832EC/IS61(4)LPS25618EC/IS61(4)VPS25618EC
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM
APRIL 2017
Features
- Internal self-timed write cycle
- Individual Byte Write Control and Global Write
- Clock controlled, registered address, data and control
- Burst sequence control using MODE input
- Three chip enable option for simple depth expansion and address pipelining
- mon data inputs and data outputs
- Auto Power-down during deselect
- Single cycle deselect
- Snooze MODE for reduced-power standby
- JEDEC 100-pin QFP, 165-ball BGA and 119- ball BGA packages
- Power supply:
LPS: VDD...
