IS67WVH16M8BLL
Overview
The IS66/67WVH16M8ALL/BLL are integrated memory device of 128Mbit Pseudo Static Random Access Memory using a self-refresh DRAM array organized as 16M words by 8 bits. The device is a dual die stack of two 64Mb die. The device supports a Hyper Bus interface, Very Low Signal Count (Address, mand and data through 8 DQ pins), Hidden Refresh Operation, and Automotive Temperature Operation, designed specially for Mobile and Automotive applications.
Distinctive Characteristics
Hyper Bus TM Low Signal Count Interface
- 3.0V I/O, 11 bus signals
- Single ended clock (CK)
- 1.8V I/O, 12 bus signals
- Differential clock (CK, CK#)
- Chip Select (CS#)
- 8-bit data bus (DQ[7:0])
- Read-Write Data Strobe (RWDS)
- Bidirectional Data Strobe / Mask
- Output at the start of all transactions to indicate refresh latency
- Output during read transactions as Read Data Strobe
- Input during write transactions as Write Data Mask
- RWDS DCARS Timing
- During read transactions RWDS is offset by a second...
