IT8893E
Overview
- PCI Express - Compliant with PCI Express Base Specification Revision 1.1 - Compliant with PCI Express to PCI/PCI-X Bridge Specification Revision 1.0 - Full 2.5GHz per direction - Data Link Layer Cyclic Redundancy Check (CRC) generator and checker - Automatic Retry of bad packets - Legacy interrupt signaling - Maximum payload size up to 256 bytes
- PCI - Compliant with PCI Local Bus Specification Revision 3.0 - Supports PCI 32-bit, 33/66 MHz, 3.3V, 5V tolerant - Supports 4(IT8892E) / 2(IT8893E) external REQ/GNT pairs for internal arbiter - Supports up to six queues for memory read cycles - Supports up to 24 outstanding memory read cycles
- Power Management - Supports PCI Express Active State Power Management (ASPM) L0s, L1 - Supports link power management state L0s, L1, L23 Ready, L2, L3 link state - Supports for PM 1.1 compatible D0, D1, D2, D3hot and D3cold device power states - Supports PME# event propagation - Supports side-band WAKE# signaling
- SPI Interface - SPI master only - Operating at up to 25MHz - Supports up to 16MB EEPROM utilizing 1, 2, or 3 byte addressing
- I/O Port 80 - Supports I/O port 80 debugging on PCI side - Dual 7-segment display
- Legacy Mode - Supports PCI-to-PCI bridge with subtractive decode for legacy devices
- Built-in Regulator - Two on-chip 3.3V to 1.8V regulators - Supports power-on-reset
- General Purpose I/O - Supports 5 GPIOs
- Package - LQFP 128
- RoHS Compliant (100% Green Available)
