HYB18T256800AF
Features
- High Performance:
-5 -400 -3.7 -533 -3S -667 -3
.. 256Mb DDR2 SDRAM
Speed Sorts DDR2 DDR2 DDR2 DDR2
-667
Units tck MHz Mb/s/pin
Bin (CL-t RCD-TRP) max. Clock Frequency Data Rate CAS Latency (CL) t RCD t RP t RAS t RC
3-3-3 200 400 3 15 15 40 55
4-4-4 266 533 4 15 15 45 60
5-5-5
4-4-4
333 667 5 15 15 45 60 4 12 12 45 57 tck ns ns ns ns
- 1.8V ± 0.1V Power Supply 1.8 V ± 0.1V (SSTL_18) patible) I/O
- DRAM organisations with 4, 8 and 16 data in/outputs
- Double Data Rate architecture: two data transfers per clock cycle, four internal banks for concurrent operation
- CAS Latency: 3, 4 and 5
- Burst Length: 4 and 8
- Differential clock inputs (CK and CK)
- Bi-directional, differential data strobes (DQS and DQS) are transmitted / received with data. Edge aligned with read data and center-aligned with write data
- DLL aligns DQ and DQS transitions with clock
- DQS can be disabled for single-ended data strobe operation
- mands entered on each positive clock edge, data and...
