HYB25D256400BT Datasheet | Infineon

Features CAS Latency and Frequency CAS Latency 2 2.5 Maximum Operating Frequency (MHz) DDR200 DDR266A DDR266 DDR333 -8 -7 -7F -6 100 133 133 133 125 143 143 166 - Double data rate architecture: two data transfers per clock cycle - Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver - DQS is edge-aligned with data for reads and is center-aligned with data for writes - Differential clock inputs (CK and CK) - Four internal banks for concurrent operation - Data mask (DM) for write data - DLL aligns DQ and DQS transitions with CK transitions - mands entered on each positive CK edge; data and data mask referenced to both edges of DQS - Burst Lengths: 2, 4, or 8 - CAS Latency: (1.5), 2, 2.5, (3) - Auto Precharge option for each burst access - Auto Refresh and Self Refresh Modes - 7.8ms Maximum Average Periodic Refresh Interval (8K refresh) - 2.5V (SSTL_2 patible) I/O - VDDQ = 2.5V ± 0.2V / VDD = 2.5V ± 0.2V - TSOP66 package - 60 balls BGA w/ 3 depop rows (“chipsize package”) 12 mm x 8 mm. Description The 256Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits. It is internally configured as a quad-bank DRAM. The 256Mb DDR SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the 256Mb DDR SDRAM effectively consists of a single 2n-bit wide, one clock cycle data transfer at the internal DRAM core and two corresponding n-bit wide, onehalf-clock-cycle data transfers at the I/O pins. A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during Reads and by the memory controller during Writes. DQS is edge-aligned with data for Reads and center-aligned...