Datasheet Details
| Part number | HYB25D256400BT |
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| Manufacturer | Infineon Technologies AG |
| File Size | 2.15 MB |
| Description | 256-Mbit Double Data Rate SDRAM |
| Datasheet |
 HYB25D256400BT Datasheet
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General Description
The 256Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits.
It is internally configured as a quad-bank DRAM.
The 256Mb DDR SDRAM uses a double-data-rate architecture to achieve high-speed operation.
Key Features
- CAS Latency and Frequency CAS Latency 2 2.5 Maximum Operating Frequency (MHz) DDR200 DDR266A DDR266 DDR333 -8 -7 -7F -6 100 133 133 133 125 143 143 166.
- Double data rate architecture: two data transfers per clock cycle.
- Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver.
- DQS is edge-aligned with data for reads and is center-aligned with data for writes.
- Differential clock inputs (CK and CK).