SAF-XC164CM-8F20F
Features
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Single cycle 16-bit CPU with 5-stage pipeline 1-cycle multiplication (16 x 16 bit), background division (32/16 bit), 1-cycle multiply-and-accumulate (MAC) instructions Zero-cycle jump execution Register-based design with multiple variable register banks Fast context switch with two additional local register banks 16 Mbytes total linear address space for code and data 1024 Bytes on-chip SFR area (C166 family patible) 16-priority-level interrupt system with up to 75 sources, sample rate down to 50 ns 8-channel interrupt-driven single-cycle data transfer facilities via peripheral event controller Clock generation via on-chip PLL or via prescaler
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2 Kbytes on-chip dual-port RAM 2 Kbytes on-chip data SRAM 2 Kbytes on-chip program/data SRAM 64 Kbytes on-chip program memory (e Flash with ECC) 14-channel A/D converter with programmable resolution and conversion time down to 2.15 µs One 16-channel general purpose capture/pare units...
