XC167CI
Features
- High Performance 16-bit CPU with 5-Stage Pipeline
- 25 ns Instruction Cycle Time at 40 MHz CPU Clock (Single-Cycle Execution)
- 1-Cycle Multiplication (16 × 16 bit), Background Division (32 / 16 bit) in 21 Cycles
- 1-Cycle Multiply-and-Accumulate (MAC) Instructions
- Enhanced Boolean Bit Manipulation Facilities
- Zero-Cycle Jump Execution
- Additional Instructions to Support HLL and Operating Systems
- Register-Based Design with Multiple Variable Register Banks
- Fast Context Switching Support with Two Additional Local Register Banks
- 16 Mbytes Total Linear Address Space for Code and Data
- 1024 Bytes On-Chip Special Function Register Area (C166 Family patible)
- 16-Priority-Level Interrupt System with 77 Sources, Sample-Rate down to 50 ns
- 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via Peripheral Event Controller (PEC), 24-Bit Pointers Cover Total Address Space
- Clock Generation via on-chip PLL (factors 1:0.15 …1:10), or via Prescaler (factors 1:1...
