SAF-C161S Overview
20 0 3 C161S 1 6 - B i t S i n g l e - C h i p M i c r o c o n t r o l l er M i c r o c o n t r o l l er s N e v e r s t o p t h i n k i n g . Edition 2003-11 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 München, Germany © Infineon Technologies AG 2004. The information herein is given to describe certain ponents and shall not be considered as a guarantee of characteristics.
SAF-C161S Key Features
- 80 ns Instruction Cycle Time at 25 MHz CPU Clock
- 400 ns Multiplication (16 × 16 bit), 800 ns Division (32 / 16 bit)
- Enhanced Boolean Bit Manipulation Facilities
- Additional Instructions to Support HLL and Operating Systems
- Register-Based Design with Multiple Variable Register Banks
- Single-Cycle Context Switching Support
- 16 Mbytes Total Linear Address Space for Code and Data
- 1024 Bytes On-Chip Special Function Register Area 16-Priority-Level Interrupt System with 30 Sources, Sample-Rate down t
