Description
and charts stated herein.
Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com).
Warnings Due to technical requirements components may contain dangerous substances.
Features
- High Performance 16-bit CPU with 4-Stage Pipeline.
- 80 ns Instruction Cycle Time at 25 MHz CPU Clock.
- 400 ns Multiplication (16 × 16 bit), 800 ns Division (32 / 16 bit).
- Enhanced Boolean Bit Manipulation Facilities.
- Additional Instructions to Support HLL and Operating Systems.
- Register-Based Design with Multiple Variable Register Banks.
- Single-Cycle Context Switching Support.
- 16 Mbytes Total Linear Address Space for Code and Data.
SAFC161S Datasheet
