CY8C6144LQI-S4F62 Datasheet | Infineon

CY8C61x4 PSo C™ 61 MCU Based on Arm® Cortex®-M4F General description PSo C™ 6 MCU is a high-performance, ultra-low-power and secured MCU platform, purpose-built for Io T applications. The CY8C61x4 product line, based on the PSo C™ 6 MCU platform, is a bination of a dual CPU microcontroller with low-power flash technology, digital programmable logic, high-performance analog-to-digital conversion and standard munication and timing peripherals. Features Note: In PSo C™ 61 the Cortex® M0+ is reserved for system functions, and is not available for applications. - 32-bit dual CPU subsystem - 150-MHz Arm® Cortex®-M4F (CM4) with single-cycle multiply (Floating Point and Memory Protection Unit) - 100-MHz Cortex®-M0+ (CM0+) with single-cycle multiply and MPU - User-selectable core logic operation at either 1.1 V or 0.9 V - Three DMA controllers - Memory subsystem - 256-KB application flash and 32-KB supervisory flash (SFlash); read-while-write (RWW) support. Two 8-KB flash caches, one for each CPU. - 128-KB SRAM with programmable power control and retention granularity - One-time-programmable (OTP) 1-Kb e Fuse array - Low-power 1.7-V to 3.6-V operation - Six power modes for fine-grained power management - Deep Sleep mode current of 7 µA with 64-KB SRAM retention - On-chip DC-DC Buck converter, < 1-µA quiescent current - Backup domain with 64 bytes of memory and real-time clock - Flexible clocking options - 8-MHz internal main oscillator (IMO) with ±2% accuracy - Ultra-low-power 32-k Hz internal low-speed oscillator (ILO) - On-chip crystal oscillators (16 MHz to 35 MHz, and 32 k Hz) - Phase-locked loop (PLL) for multiplying clock frequency - Frequency-locked loop (FLL) for multiplying IMO frequency - Quad-SPI (QSPI)/Serial Memory Interface (SMIF) - Execute-In-Place (XIP) from external Quad SPI Flash - On-the-fly encryption and...