CYT2B97BAS Datasheet | Infineon

CYT2B9 32-bit Arm® Cortex®-M4F microcontroller TRAVEO™ T2G family General description CYT2B9 is a family of TRAVEO™ T2G microcontrollers targeted at automotive systems such as body control units. CYT2B9 has an Arm® Cortex®-M4 CPU for primary processing, and an Arm® Cortex®-M0+ CPU for peripheral and security processing. These devices contain embedded peripherals supporting Controller Area Network with Flexible Data rate (CAN FD), Local Interconnect Network (LIN), and Clock Extension Peripheral Interface (CXPI). TRAVEO™ T2G devices are manufactured on an advanced 40-nm process. CYT2B9 incorporates Cypress' low-power flash memory, multiple high-performance analog and digital peripherals, and enables the creation of a secure puting platform. Features - Dual CPU subsystem - 160-MHz (max) 32-bit Arm® Cortex®-M4F CPU with - Single-cycle multiply - Single-precision floating point unit (FPU) - Memory protection unit (MPU) - 100-MHz (max) 32-bit Arm® Cortex® M0+ CPU with - Single-cycle multiply - Memory protection unit - Inter-processor munication in hardware - Three DMA controllers - Peripheral DMA controller #0 (P-DMA0) with 92 channels - Peripheral DMA controller #1 (P-DMA1) with 44 channels - Memory DMA controller #0 (M-DMA0) with 4 channels - Integrated memories - 2112-KB of code-flash with an additional 128-KB of work-flash - Read-While-Write (RWW) allows updating the code-flash/work-flash while executing code from it - Single- and dual-bank modes (specifically for Firmware update Over The Air [FOTA]) - Flash programming through SWD/JTAG interface - 256-KB of SRAM with selectable retention granularity - Crypto engine[1] - Supports Enhanced Secure Hardware Extension (e SHE) and Hardware Security Module (HSM) - Secure boot and authentication - Using digital signature verification - Using fast secure boot - AES: 128-bit blocks, 128-/192-/256-bit...