CYT2BL3BAS Key Features
- Dual CPU subsystem
- Single-cycle multiply
- Single-precision floating point unit (FPU)
- Memory protection unit (MPU)
- Single-cycle multiply
- Memory protection unit
- Inter-processor munication in hardware
- Three DMA controllers
- Peripheral DMA controller #0 (P-DMA0) with 92 channels
- Peripheral DMA controller #1 (P-DMA1) with 44 channels