Datasheet4U Logo Datasheet4U.com

ESD102-U4-05L - Transient Voltage Suppressor Diodes

General Description

Pin 5 Pin 4 Pin 1 Pin 3 Pin 4 Pin 5 I/O I/O I/O I/O Pin 1 Pin 2 Pin 3 a) Pin configuration GND Pin 2 b) Schematic diagram Figure 1 Pin Configuration and Schematic Diagram Table 1 Ordering Information Type Package ESD102-U4-05L TSLP-5-2 Configuration 4 lines, uni-directional Final Data Sh

Key Features

  • ESD / transient protection of high speed data lines exceeding:.
  • IEC61000-4-2 (ESD): ±24 kV (air), ±20 kV (contact).
  • IEC61000-4-4 (EFT): ±60 A / ±3 kV (5/50ns).
  • IEC61000-4-5 (Surge): ±3.5 A (8/20μs).
  • Maximum working voltage: VRWM = 3.3 V.
  • Ultra low capacitance:.
  • CL = 0.2 pF I/O to I/O (typical).
  • CL = 0.4 pF I/O to GND (typical).
  • Extremely low leakage voltage: 1 nA (typical).
  • Very low clamping voltage: VCL =.

📥 Download Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
TVS Diodes Transient Voltage Suppressor Diodes ESD102-U4-05L Ultra-Low Capacitance ESD Protection Array for Flow-Through PCB Layout ESD102-U4-05L Data Sheet Revision 1.0, 2013-02-25 Final Power Management & Multimarket Edition 2013-02-25 Published by Infineon Technologies AG 81726 Munich, Germany © 2013 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics.