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ESD3V3U4ULC - Transient Voltage Suppressor Diodes

General Description

Pin 9 Pin 8 Pin 7 Pin 6 Pin 1 I/O Pin 2 I/O Pin 4 I/O Pin 5 I/O GND Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 3 b) Schematic diagram a) Pin configuration Figure 1 Table 1 Type ESD3V3U4ULC Pin Configuration and Schematic Diagram Ordering Information Package TSLP-9-1 Configuration 4 lines, uni

Key Features

  • 0-4-4 (EFT) : 2.5 kV (5/50ns).
  • IEC61000-4-5 (Surge) : 3 A (8/20μs) Maximum working voltage: VRWM = 3.3 V Ultra low capacitance CL = 0.4 pF I/O to GND (typical) Very low clamping voltage: VCL = 8 V at IPP = 16 A (typical) Very low dynamic resistance: RDYN = 0.19 Ω (typical) TSLP-9-1 package with pad pitch 0.5 mm, optimized pad design to simplify PCB layout Pb-free and halogen free package (RoHS compliant) 1.2.

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Datasheet Details

Part number ESD3V3U4ULC
Manufacturer Infineon
File Size 1.08 MB
Description Transient Voltage Suppressor Diodes
Datasheet download datasheet ESD3V3U4ULC Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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TVS Diodes Transient Voltage Suppressor Diodes ESD3V3U4ULC Ultra-low Capacitance ESD / Transient Protection Array ESD3V3U4ULC Data Sheet Rev. 1.2, 2012-07-03 Final Power Management & Multimarket Free Datasheet http://www.Datasheet4U.com Edition 2012-07-03 Published by Infineon Technologies AG 81726 Munich, Germany © 2012 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics.