Infineon Technologies HYB18H256321AFL20
The HYB18H256321AF[L] operates from a differential clock (CLK and CLK).| Part No. | HYB18H256321AFL20 |
|---|---|
| Datasheet | HYB18H256321AFL20 Download |
| Manufacturer |  Infineon Technologies |
| Description | 256-Mbit x32 GDDR3 DRAM |
| Buy | Stock & Price |
FEATURES
● 2.0 V VDDQ IO voltage (HYB18H256321AF–12/14/16)● 2.0 V VDD core voltage (HYB18H256321AF–12/14/16)
● 1.8 V VDDQ IO voltage (HYB18H256321AFL14/16/20)
● 1.8 V VDD core voltage (HYB18H256321AFL14/16/20)
● Organization: 2048K × 32 × 4 banks
● 4096 rows and 512 columns (128 burst start locations) per bank
● Differential clock inputs (CLK and CLK)
● CAS latencies of 7 8, 9, 10, 11
● Write latencies of 3, 4
● Burst sequence with length of 4, 8.
● 4n pre fetch
● Short RAS to CAS timing for Writes
● tRAS Lockout support
● tWR programmable for Writes with Auto-Precharge
● Data mask for write commands
● Single ended READ strobe (RDQS) per byte. RDQS edge-aligned with READ data
● Single ended WRITE strobe (WDQS) per byte. WDQS center-aligned with WRITE data
● DLL aligns RDQS and DQ transitions with Clock
● Programmable IO interface including on chip termination (ODT)
● Autoprecharge option with concurrent auto precharge support
● 4k Refresh (32ms)
● Autorefresh and Self Refresh
● PG-TFBGA 136 package (11mm × 14mm)
● Calibrated output drive.
