Infineon Technologies HYB25D128323C-L3.6
The Infineon 128Mbit DDR SGRAM is a ultra high performance graphics memory device, designed to meet all requirements for high bandwidth intensive applications like PC graphics systems. The 128Mbit DDR SGRAM uses a double-data-rate DRAM architecture organized as 4 banks × 4096 rows × 256 columns × 32 bits.| Part No. | HYB25D128323C-L3.6 |
|---|---|
| Datasheet | HYB25D128323C-L3.6 Download |
| Manufacturer |  Infineon Technologies |
| Description | 128 Mbit DDR SGRAM |
| Buy | Stock & Price |
FEATURES
● Maximum clock frequency up to 333 MHz● Maximum data rate up to 666 Mbps/pin
● Data transfer on both edges of clock
● Programmable CAS latency of 2, 3 and 4 clocks
● Programmable burst length of 2, 4 and 8
● Integrated DLL to align DQS and DQ transitions with CLK
● Data transfer signals are synchronized with byte wise bidirectional Data Strobe
● Data Strobe signal edge-aligned with data for Read operations
● Data Strobe signal center aligned with data for Write operations
● Differential clock inputs (CLK and CLK)
● Data mask for masking write data, one DM per byte
● Organization 1024K × 32 × 4 banks
● 4096 rows and 256 columns per bank
● 4K Refresh (32ms)
● Refresh Interval 7.8 µsec
● Autorefresh and Self Refresh available
● Standard JEDEC TF-XBGA 128 package
● Self-mirrored, symmetrical ball out
● Matched Impedance Mode interface (Z0=60Ω)
● SSTL-2 JEDEC Weak Mode interface (Z0=34Ω)
● IO voltage VDDQ = 2.5 V
● VDD power supply memory core: – Speed sorts –3 and –3.3: 2.5 V <...
