DESCRIPTION
of register bits SIDLE, SAISA, RDC extended. 91, 101, 113, 118, 127, 151, 154 DESCRIPTION
of register bits OD, XBIT, GN, RES, T1E1 corrected. 167, 179 Major parts of register description (FHND and PHND) rewritten. Register FHND: Bits ABORT and XTF removed. Register PHND: Bit XTF removed. 177 Removed register bit XRA. 191 Section ’DMA Interface Signals’ added. 204 RTD is updated with rising edge of RTC. This is corrected in Figure 49. Some minor documentation updates (wording, syntax, ...). Name change M13FX -> TE3-MUX. Removed PEF version. Corrected Table 27 "DS1/E1 Receive Data Timing" on Page 202. Changed figure 25 and 27. Removed timing 35. Changed timings 101,111,151,152,195,198. Changed table 11. Changed FEAC FHND register to contain XTF bit. For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see our webpage at PEB 3445 E 1 1.1 1.1.1 1.1.2 1.1...
Infineon Technologies
