PEF22554
Overview
- Additional automatic resynchronization mode for T1 (new bit: FMR2.7 = AFRS).
- Additional compare status field (mode 2) in SS7 mode (new bit: CCR5.6 = CSF2).
- 2048 kHz synchronization interface according o ITU-T G.703 Sec. 13 (E1). For more information refer to online Application Notes
- 2 Correction of Errata All severe errata of QuadFALC® Version 1.3 have been fixed. For more information please contact your local sales office.
- 3 Modified Pin Functions QuadFALC® Version 2.1 is pin-compatible with QuadFALC® Version 1.x. However, some pin functions have been modified as detailed below:
- No 5 V input levels are allowed due to technology restrictions (see Page 24).
- The currently unused ("N.C.") pins on V1.3 devices are used as "Core Voltage Supply" (VDDC) pins and "Voltage Selection" (VSEL) pin on V2.x devices. Due to the new technology the core voltage is 1.8 V (see Chapter 1.5).
- 4 Package In addition to the P-TQFP-144-8 package, a P-BGA-160-1 package with a ball pitch of 1.0 mm and a size of 15 mm × 15 mm is supported (see Figure 4).
- 5 Power Supply The Version 2.1 device requires two supply voltages, 3.3 V and 1.8 V. For compatibility reasons, it is possible to operate the device off a single 3.3 V supply, with the 1.8 V Delta Sheet 2/30
