PEF3460E Datasheet PDF

FEATURES

GENERAL FEATURES

● Integrated T3/E3 LIU for recovery of analog signals from the line and the transmission of signals onto the line via a transformer.
● Flexible main clock input accepting any frequency between 4 and 52 MHz. P-BGA-272-4
● Integrated transmit and receive jitter attenuators
● Integrated transmit clock multiplier to enable a wide number of transmit reference clocks (optional) to be used from 8 kHz to 52 MHz
● Integrated receive clock multiplier to enable a wide number of receive reference clocks (optional) to be used from 8 kHz to 52 MHz
● Integrated receive reference clock multiplier
● DS3 M23 and C-Bit Parity framer with overhead bit processing.
● E3 G.832 framer with overhead byte processing.
● E3 G.751 framer with overhead bit processing.
● Integrated Bit Error Rate Tester (BERT)
● ATM TC layer allowing the direct mapping/extraction of ATM cells into/from the DS3 or E3 frame.
● ATM DS3/E3 G.751 PLCP function allowing the mapping of ATM cells into the DS3/ E3 G.751 frame using the PLCP sub-frame.