Description
The FL-L family devices are flash non-volatile memory products using:
Floating gate technology
65-nm process lithography The FL-L family connects to a host system via a serial peripheral interface (SPI).
Features
- a page programming buffer that allows up to 256-bytes to be programmed in one operation and provides individual 4KB sector, 32KB half block, 64KB block, or entire chip erase. By using FL-L family devices at the higher clock rates supported, with Quad commands, the instruction read transfer rate can match or exceed traditional parallel interface, asynchronous, NOR flash memories, while reducing signal count dramatically. The FL-L family products offer high densities coupled with the flexibility a.
S25FL256L Datasheet
