S26HL256T
Features
- Infineon 45-nm MIRRORBIT™ technology that stores two data bits in each memory array cell
- Sector architecture options
- Uniform: Address space consists of all 256KB sectors
- Hybrid
- Configuration 1: Address space consists of thirty-two 4KB sectors grouped either on the top or the bottom while the remaining sectors are all 256KB
- Configuration 2: Address space consists of thirty-two 4KB sectors equally split between top and bottom while the remaining sectors are all 256KB
- Page Programming buffer of 256 or 512 bytes
- OTP secure silicon region (SSR) of 1024 bytes (32 × 32 bytes)
- HYPERBUS™ interface
- JEDEC e Xpanded SPI (JESD251) patible
- DDR option runs up to 400-MBps (200 MHz clock speed)
- Supports data strobe (DS) to simplify the read data capture in high-speed systems
- Legacy (x1) SPI (1S-1S-1S)
- JEDEC e Xpanded SPI (JESD251) patible
- SDR option runs up to 21-MBps (166 MHz clock speed)
- SEMPER™ Flash with HYPERBUS™ interface devices support default boot in...
