S26HS04GT
overview
- Architecture
- Infineon® 45-nm MIRRORBIT™ technology that stores two data bits in each memory array cell
- Multi-chip package (MCP)
- 02GT Dual die package (DDP) 2 1 Gb die
- 04GT Quad die package (QDP) 4 1 Gb die
- Sector architecture options
- Uniform: Address space consists of all 256 KB sectors
- Hybrid Configuration 1: Address space consists of thirty-two 4 KB sectors grouped either on the top or the bottom while the remaining sectors are all 256 KB Configuration 2: Address space consists of thirty-two 4 KB sectors at the top and bottom while the remaining sectors are all 256 KB
- Page programming buffer of 256 or 512 bytes
- OTP secure silicon region (SSR) of 1024-bytes (32 32 bytes)
- Interface
- HYPERBUS™ interface
- JEDEC e Xpanded SPI (JESD251) pliant
- DDR option runs up to 332 MBps (166 MHz clock speed)
- Supports data strobe (DS) to simplify the read data capture in high-speed systems
- Legacy (×1) SPI (1S-1S-1S)
- JEDEC e Xpanded SPI (JESD251) pliant
- SDR...
