S26KL256S Datasheet PDF

FEATURES

● 3.0 V I/O, 11 bus signals - Single ended clock
● 1.8 V I/O, 12 bus signals - Differential clock (CK, CK#)
● Chip Select (CS#)
● 8-bit data bus (DQ[7:0])
● Read-write data strobe (RWDS) - HYPERFLASH™ memories use RWDS only as a Read Data Strobe
● Up to 333-MBps sustained read throughput
● DDR: two data transfers per clock
● 166-MHz clock rate (333 MBps) at 1.8 V VCC
● 100-MHz clock rate (200 MBps) at 3.0 V VCC
● 96-ns initial random read access time - Initial random access read latency: 5 to 16 clock cycles
● Sequential burst transactions
● Configurable burst characteristics - Wrapped burst lengths:
● 16 bytes (8 clocks)
● 32 bytes (16 clocks)
● 64 bytes (32 clocks) - Linear burst - Hybrid option: one wrapped burst followed by linear burst - Wrapped or linear burst type selected in each transaction - Configurable output drive strength
● Low power modes - Active clock stop during read: 12 mA, no wake-up required - Standby: 25 µA (typical), no wake-up required - Deep Power-Down...