S28HL01GT
Features
- Infineon 45-nm MIRRORBIT™ technology that stores two data bits in each memory array cell
- Sector architecture options
- Uniform: Address space consists of all 256KB sectors
- Hybrid:
- Configuration 1
- Address space consists of thirty-two 4 KB sectors grouped either on the top or the bottom while the remaining sectors are all 256KB
- Configuration 2
- Address space consists of thirty-two 4 KB sectors equally split between top and bottom while the remaining sectors are all 256KB
- Page programming buffer of 256 or 512 bytes
- OTP secure silicon array of 1024 bytes (32 32 bytes)
- Octal interface (8S-8S-8S, 8D-8D-8D)
- JEDEC e Xpanded serial peripheral interface (SPI) (JESD251) pliant
- SDR option runs up to 200-MBps (200 MHz clock speed)
- DDR option runs up to 400-MBps (200 MHz clock speed)
- Supports data strobe (DS) to simplify the read data capture in high-speed systems
- Functional safety features
- Functional safety ISO26262 ASIL B pliant and ASIL D ready
- Infineon...
