S28HS512T Datasheet

S28HS512T Key Features

• Infineon 45-nm MIRRORBIT™ technology that stores two data bits in each memory array cell
• Sector architecture options
• Uniform: Address space consists of all 256KB sectors
• Hybrid
• Configuration 1
• Address space consists of thirty-two 4 KB sectors grouped either on the top or the bottom while the remaining sectors ar
• Configuration 2
• Address space consists of thirty-two 4 KB sectors equally split between top and bottom while the remaining sectors are a
• Page programming buffer of 256 or 512 bytes
• OTP secure silicon array of 1024 bytes (32  32 bytes)