S70FL01GS
Key Features
- CMOS 3.0 V Core
- Serial peripheral interface (SPI) with Multi-I/O - SPI clock polarity and phase modes 0 and 3 - Double data rate (DDR) option - Extended addressing: 32-bit address - Serial command set and footprint compatible with S25FL-A, S25FL-K, and S25FL-P SPI families - Multi I/O command set and footprint compatible with S25FL-P SPI family
- READ commands - Normal, Fast, Dual, Quad, Fast DDR, Dual DDR, Quad DDR - AutoBoot - power up or reset and execute a Normal or Quad read command automatically at a preselected address - Common flash interface (CFI) data for configuration information
- Programming (1.5 Mbytes/s) - 512-byte page programming buffer - Quad-input page programming (QPP) for slow clock systems
- Erase (0.5 Mbytes/s) - Uniform 256-kbyte sectors
- Cycling endurance - 100,000 program-erase cycles, minimum
- Data retention - 20-year data retention, minimum
- Security features - One time program (OTP) array of 2048 bytes - Block protection
- Status register bits to control protection against program or erase of a contiguous range of sectors.
- Hardware and software control options
