DESCRIPTION
Early steering output. Presents a logic high immediately when the digital algorithm detects a recognizable tone-pair (signal condition). Any momentary loss of signal condition will cause ESt to return to a logic low. Gain Select. Gives access to output of front-end differential amplifier for connection of feedback resistor. Internal Connection. Must be tied to GND. Non-Inverting Input Inverting Input Clock Input Clock Output Connections to the front-end differential amplifier. 3.579545 MHz crystal connected between these pins completes internal oscillator. GS IC IN+ INC1 C2 Q1-Q4 StD 3 5,6 1 2 7 8 11-14 15 3-state data outputs. When enabled by OE, provide the code corresponding to the last valid tone-pair received. Delayed steering output. Presents a logic high when a received tone-pair has been registered and the output latch updated; returns to logic low when the voltage on St/GT falls below VTSt. Steering input/guard time output (bi-directional). A voltage greater than VTSt, detected at St causes the device to register the detected tone-pair and update the output latch.
Integral
