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IS61SF6432 - 64K x 32 SYNCHRONOUS FLOW-THROUGH STATIC RAM

Download the IS61SF6432 datasheet PDF. This datasheet also covers the IS6 variant, as both devices belong to the same 64k x 32 synchronous flow-through static ram family and are provided as variant models within a single manufacturer datasheet.

General Description

The ICSI IS61SF6432 is a high-speed, low-power synchronous static RAM designed to provide a burstable, high-performance, secondary cache for the Pentium™, 680X0™, and PowerPC™ microprocessors.

It is organized as 65,536 words by 32 bits, fabricated with ICSI's advanced CMOS technology.

Key Features

  • Fast access time: 9 ns, 10 ns Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Pentium™ or linear burst sequence control using MODE input Three chip enables for simple depth expansion and address pipelining Common data inputs and data outputs Power-down control by ZZ input JEDEC 100-Pin LQFP an.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (IS6-1SF6.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number IS61SF6432
Manufacturer Integrated Circuit Solution Inc
File Size 480.70 KB
Description 64K x 32 SYNCHRONOUS FLOW-THROUGH STATIC RAM
Datasheet download datasheet IS61SF6432 Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
IS61SF6432 IS61SF6432 64K x 32 SYNCHRONOUS FLOW-THROUGH STATIC RAM FEATURES • • • • • • • • • • • • Fast access time: 9 ns, 10 ns Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Pentium™ or linear burst sequence control using MODE input Three chip enables for simple depth expansion and address pipelining Common data inputs and data outputs Power-down control by ZZ input JEDEC 100-Pin LQFP and PQFP package Single +3.3V power supply Two Clock enables and one Clock disable to eliminate multiple bank bus contention.