IC61C256AH Datasheet | Integrated Circuit Solution

Document Title 32K x 8 High Speed SRAM Revision History Revision No 0A 0B 0C 0D History Initial Draft Revise typo of t HA on page 7 Add SOP package type Revise typo of sop size at page 2,9 Draft Date March 23,2001 October 18,2001 February 18,2002 April 19,2002 Remark The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices. Integrated Circuit Solution Inc. AHSR010-0D 4/19/2002 32K x 8 HIGH-SPEED CMOS STATIC RAM Features - High-speed access times: 10, 12, 15, 20, 25 ns - Low active power: 400 m W (typical) - Low standby power -- 250 µW (typical) CMOS standby -- 55 m W (typical) TTL standby - Fully static operation: no clock or refresh required - TTL patible interface and outputs - Single 5V power supply DESCRIPTION The ICSI IC61C256AH is very high-speed, low power, 32,768 word by 8-bit static RAMs. They are fabricated using ICSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields access times as fast as 8 ns maximum. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation is reduced to 50 µW (typical) with CMOS input levels. Easy memory expansion is provided by using an active LOW Chip Enable (CE). The active LOW Write Enable (WE) controls both writing and reading of the memory. The IC61C256AH is pin patible with other 32k x 8 SRAMs and are available in 28-pin 300mil PDIP, 300mil SOJ, and 8- 13.4mm TSOP-1 package, 330 mil SOP. FUNCTIONAL BLOCK DIAGRAM A0-A14 DECODER 32K X 8 MEMORY ARRAY VCC GND I/O DATA CIRCUIT I/O0-I/O7 COLUMN I/O CE OE WE CONTROL...