ICS855011 Datasheet | Integrated Circuit System

PRELIMINARY Integrated Circuit Systems, Inc. .. LOW SKEW , 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V CML FANOUT BUFFER GENERAL DESCRIPTION The ICS855011 is a low skew, high performance 1-to-2 Differential-to-2.5V/3.3V CML Hi Per Clock S™ Fa n o u t B u f fe r a n d a m e m b e r o f t h e Hi Per Clock S ™ family of High Perfor mance Clock Solutions from ICS. The ICS855011 is characterized to operate from either a 2.5V or a 3.3V power supply. Guaranteed output and par t-to-par t skew characteristics make the ICS855011 ideal for those clock distribution applications demanding well defined perfor mance and repeatability. Features - 2 differential 2.5V/3.3V CML outputs - 1 differential PCLK, n PCLK input pair - PCLK, n PCLK pair can accept the following differential input levels: LVPECL, LVDS, CML, SSTL - Output frequency: >3GHz - Translates any single ended input signal to 3.3V LVPECL levels with resistor bias on n PCLK input - Output skew: 5ps (typical) - Part-to-part skew: TBD - Propagation delay: 242ps (typical) - Operating voltage supply range: VCC = 2.375V to 3.8V, VEE = 0V - -40°C to 85°C ambient operating temperature BLOCK DIAGRAM PCLK n PCLK Q0 n Q0 Q1 n Q1 PIN ASSIGNMENT Q0 n Q0 Q1 n Q1 1 2 3 4 8 7 6 5 Vcc PCLK n PCLK VEE 8-Lead SOIC 3.90mm x 4.90mm x 1.37mm package body M Package Top View The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 855011AM .icst./products/hiperclocks.html REV. A AUGUST 18, 2004 PRELIMINARY Integrated Circuit Systems, Inc. .. LOW SKEW , 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V CML FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS Number 1, 2 3, 4 5 6 7 8 Name Q0, n Q0 Q1, n Q1 VEE n PCLK PCLK VCC Output Output Power Input Input Power Pullup Type...