AV9107C-17 Datasheet | Integrated Circuit Systems

Description The AV9107C-17 offers a tiny footprint solution for generating two simultaneous clocks. One clock, the REFCLK, is a fixed output frequency which is the same as the input reference crystal (or clock). The other clock, CLK1, can vary between 25.06 and 33.29 MHz. The device has advanced features which include on-chip loop filters, tristate outputs, and power-down capability. A mini-mum of external ponents - two decoupling capacitors and an optional ferrite bead - are all that are required for jitter-free operation. Features - - - - - - - - Patented on-chip Phase-Locked Loop with VCO for clock generation Provides reference clock and synthesized clock Generates frequencies of 25 and 33 MHz 8-pin DIP or SOIC package 14.318 MHz input reference frequency On-chip loop filter Low power CMOS technology Single +3.3 or +5 volt power supply Applications puter: The AV9107C-17 is the ideal solution for replacing high speed oscillators and for reducing clock speeds to save power in puters. The device provides smooth, glitch-free frequency transitions so that the CPU can continue to operate during slow down or speed up. The rate of frequency change makes the AV9107C-17 patible with all 386DX, 386SX, 486DX, 486DX2, and 486SX devices. Block Diagram AV 9107-17 Rev C052197P Pin Configuration Functionality (at 14.318) MHz reference frequency input) FS 0 1 CLK1 25.06 MHz 33.29 MHz 8-Pin DIP, SOIC Pin Descriptions PIN NUMBER 1 2 3 4 5 6 7 8 PIN NAME FS0 GND X1/ICLK X2 OE CLK1 VDD REFCLK TYPE Input Input DESCRIPTION Frequency Select 0 for CLK1. Digital Ground. Crystal Output or Input Clock frequency. Typically 14.318 MHz system clock. Output Crystal Output (No Connect when clock used.). Input Output Enable. Tristates CLK1 and REFCLK when low. Has internal pull-up. Output Clock 1 Output (see decoding tables). Digital power supply (+5V DC). Reference Clock output. Produces a buffered version of the input clock or crystal frequency Output (typically 14.318 MHz). -...