ICS181-53 Overview
The ICS181-53 generates a low EMI output clock from a clock or crystal input. The device uses ICS’ proprietary mix of analog and digital Phase Locked Loop (PLL) technology to spread the frequency spectrum of the output, thereby reducing the frequency amplitude peaks by several dB. The ICS181-53 offers center spread selection of +/-0.625% and +/-1.875%.
ICS181-53 Key Features
- Pin and function patible to Cypress W181-53 Packaged in 8-pin SOIC Provides a spread spectrum output clock Accepts a clo
- Input frequency of 46 to 75 MHz for Clock input
- Peak reduction by 7dB
- 14dB typical on 3rd
- Spread percentage selection for +/-0.625% and
- Operating voltage of 3.3 V and 5 V
- Advanced, low-power CMOS process
- Power Input Output Power Input Input