ICS2509C - 3.3V Phase-Lock Loop Clock Driver

Product Overview

Integrated Circuit Systems

Part number	ICS2509C
Manufacturer	Integrated Circuit Systems
File Size	248.21 KB
Description	3.3V Phase-Lock Loop Clock Driver
Datasheet	ICS2509C Datasheet
Additional preview pages of the ICS2509C datasheet.

The ICS2509C is a high performance, low skew, low jitter clock driver.

It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the CLKIN signal with the CLKOUT signal.

It is specifically designed for use with synchronous SDRAMs.

Meets or exceeds PC133 registered DIMM specification 1.1 Spread Spectrum Clock Compatible Distributes one clock input to one bank of five and one bank of four outputs Separate output enable(OEA,OEB) for each output bank Operating frequency 25 MHz to 175 Mhz External feedback input (FBIN) terminal is used to synchrionize the outputs to the clock input No external RC network required Operates at 3.3V Vcc Plas.

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Published: Jan 13, 2006 |