Datasheet4U Logo Datasheet4U.com

ICS527-04 - Clock Slicer User Configurable PECL input Zero Delay Buffer

Datasheet Summary

Description

The ICS527-04 Clock Slicer is the most flexible way to generate an output clock from an input clock with zero skew.

The user can easily configure the device to produce nearly any output clock that is multiplied or divided from the input clock.

Features

  • Packaged as 28-pin SSOP (150 mil body) Synchronizes fractional clocks rising edges CMOS in to PECL out PECL in to PECL out Pin selectable dividers Zero input to output skew User determines the output frequency - no software needed Slices frequency or period Input clock frequency of 1.5 MHz - 200 MHz Output clock frequencies up to 160 MHz Very low jitter Duty.

📥 Download Datasheet

Datasheet preview – ICS527-04

Datasheet Details

Part number ICS527-04
Manufacturer Integrated Circuit Systems
File Size 206.43 KB
Description Clock Slicer User Configurable PECL input Zero Delay Buffer
Datasheet download datasheet ICS527-04 Datasheet
Additional preview pages of the ICS527-04 datasheet.

📁 Similar Datasheet

  • ICS527-04 - Clock Slicer (Renesas)
  • ICS527-02 - CLOCK SLICER USER CONFIGURABLE PECL INPUT ZERO DELAY BUFFER (Renesas)
  • ICS527-03 - CLOCK SLICER USER CONFIGURABLE PECL OUTPUT ZDB (Renesas)
  • ICS524 - LOW SKEW 1 TO 4 CLOCK BUFFER (Integrated Device Technology)
  • ICS524 - LOW SKEW 1 TO 4 CLOCK BUFFER (Renesas)
  • ICS525-01 - USER CONFIGURABLE CLOCK (IDT)
  • ICS525-02 - USER CONFIGURABLE CLOCK (IDT)
  • ICS501 - PLL CLOCK MULTIPLIER (IDT)
  • ICS501 - PLL CLOCK MULTIPLIER (Renesas)
  • ICS501A - PLL CLOCK MULTIPLIER (Renesas)
Other Datasheets by Integrated Circuit Systems
  • ICS527-01 - User Configurable Zero Delay Buffer
  • ICS527-02 - Clock Slicer User Configurable PECL Input Zero Delay Buffer
  • ICS527-03 - Clock Slicer User Configurable PECL Output Zero Delay Buffer
  • ICS525-01 - (ICS525-01/02) User Configurable Clock
  • ICS525-02 - (ICS525-01/02) User Configurable Clock
  • ICS525-03 - PECL Input OSCaR-TM USER Configurable Clock
  • ICS525-04 - OSCaR-TM User Configurable PECL Clock
  • ICS525-11 - (ICS525-11/12) User Configurable Clock

Full PDF Text Transcription

Click to expand full text
www.DataSheet4U.com ICS527-04 Clock Slicer User Configurable PECL input Zero Delay Buffer Description The ICS527-04 Clock Slicer is the most flexible way to generate an output clock from an input clock with zero skew. The user can easily configure the device to produce nearly any output clock that is multiplied or divided from the input clock. The part supports non-integer multiplications and divisions. Using Phase-Locked Loop (PLL) techniques, the device accepts an input clock up to 200 MHz and produces an output clock up to 160 MHz. The ICS527-04 aligns rising edges on PECLIN with FBPECL at a ratio determined by the reference and feedback dividers. For other PECL output clocks, see the ICS507-01, ICS525-03, or the MK3707. For PECL in and CMOS out, see the ICS527-02.
Published: |