ICS83026I-01 Datasheet | Integrated Circuit Systems

Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER Features - Two LVCMOS / LVTTL outputs - Differential CLK, n CLK input pair - CLK, n CLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL - Maximum output frequency: 350MHz - Output skew: 15ps (maximum) - Part-to-part skew: 600ps (maximum) - Additive phase jitter, RMS: 0.03ps (typical) - Small 8 lead SOIC package saves board space - 3.3V core, 3.3V, 2.5V or 1.8V output operating supply - -40°C to 85°C ambient operating temperature - Available in both standard and lead-free Ro HS pliant packages GENERAL DESCRIPTION The ICS83026I-01 is a low skew, 1-to-2 Differential-to-LVCMOS/LVTTL Fanout Buffer and Hi Per Clock S™ a member of the Hi Per Clock S ™ family of High Perfor mance Clock Solutions from ICS. The differential input can accept most differential signal types (LVPECL, LVDS, LVHSTL, HCSL and SSTL) and translate to two single-ended LVCMOS/LVTTL outputs. The small 8-lead SOIC footprint makes this device ideal for use in applications with limited board space. .. IC S BLOCK DIAGRAM PIN ASSIGNMENT VDD CLK n CLK OE 1 2 3 4 8 7 6 5 VDDO Q0 Q1 GND Q0 CLK n CLK Q1 OE 8-Lead SOIC 3.8mm x 4.8mm, x 1.47mm package body M Package Top View VDD CLK n CLK OE 1 2 3 4 8 7 6 5 VDDO Q0 Q1 GND 8-Lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Top View 83026BMI-01 .icst./products/hiperclocks.html REV. A JANUARY 16,...