ICS83948I-147 Datasheet | Integrated Circuit Systems

Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-12 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER Features - Twelve LVCMOS/LVTTL outputs - Selectable LVCMOS/LVTTL clock or differential CLK, n CLK inputs - CLK, n CLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL - LVCMOS_CLK accepts the following input levels: LVCMOS or LVTTL - Output frequency: 350MHz (maximum) - Output skew (at 3.3V ± 5%): 100ps (maximum) - Part-to-part skew (at 3.3V ± 5%): 1ns (maximum) - Full 3.3V or full 2.5V operating supply - -40°C to 85°C ambient operating temperature - Available in both standard and lead-free Ro HS-pliant packages GENERAL DESCRIPTION The ICS83948I-147 is a low skew, 1-to-12 Differential-to-LVCMOS/LVTTL Fanout Buffer and Hi Per Clock S™ a member of the Hi Per Clock S™ family of High Performance Clock Solutions from ICS. The ICS83948I-147 has two selectable clock inputs. The CLK, n CLK pair can accept most standard differential input levels. The LVCMOS_CLK can accept LVCMOS or LVTTL input levels. The low impedance LVCMOS/LVTTL outputs are designed to drive 50Ω series or parallel terminated .. transmission lines. The effective fanout can be increased from 12 to 24 by utilizing the ability of the outputs to drive two series terminated lines. IC S The ICS83948I-147 is characterized at full 3.3V or full 2.5V operating supply modes. Guaranteed output and part-to-part skew characteristics make the ICS83948I-147 ideal for those clock distribution applications demanding well defined performance and repeatability. BLOCK DIAGRAM CLK_EN D Q LE LVCMOS_CLK CLK n CLK 1 Q0 0 Q1 CLK_SEL Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 OE PIN ASSIGNMENT GND GND VDDO VDDO Q0 Q1 Q2 Q3 32 31 30 29 28 27 26 25 CLK_SEL LVCMOS_CLK CLK n CLK CLK_EN OE VDD GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Q11 VDDO Q10 GND Q9 VDDO Q8 GND 24 23 22 GND Q4 VDDO Q5 GND Q6 VDDO Q7 21 20 19 18 17 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y...