ICS839893I Datasheet | Integrated Circuit Systems

Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-13 LVCMOS/LVTTL BUFFER DIVIDER Features - 13 LVCMOS/LVTTL outputs: 3 banks (6, 6, 1 outputs per bank respectively) - Selectable CLK0 or CLK1 LVCMOS/LVTTL clock inputs - CLK0, CLK1 supports the following input types: LVCMOS, LVTTL - Maximum output frequency: 250MHz - Output skew: 40ps (maximum), within bank - Full 3.3V or 2.5V operating supply - -40°C to 85°C ambient operating temperature - Available in both, Standard and Ro HS/Lead-Free pliant packages GENERAL DESCRIPTION The ICS839893I is a high-performance one to thirteen LVCMOS/LVTTL buffer/divider and is Hi Per Clock S™ a member of the Hi Per Clock S™ family of High Performance Clock Solutions from ICS. The device has two selectable LVCMOS/LVTTL clock inputs and it generates 13 new LVCMOS/LVTTL clock outputs. The first bank of six outputs offers divide-by-1, 2, 4, 8 or 16. The second bank of six outputs can be configured to as the first bank, or with an additional w w w . D a t the a S same h e e divide t 4 U . ratio c o m divide-by-two. The first two banks can be placed into a highimpedance output state with the assertion of a LOW on the n OE/MR input. One additional output can be configured to divide-by-4, 6, 8 or 16. This device is functional with full 3.3V or full 2.5V supplies. IC S SIMPLIFIED BLOCK DIAGRAM n OE/MR PIN ASSIGNMENT V DD nc REF_SEL nc GND FSEL0 FSEL1 GND FSEL2 FSEL3 n OE/MR V DD FSEL0 FSEL0 FSEL1 FSEL1 FSEL2 FSEL2QAQA 0 0 0 ÷1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 ÷1 ÷2 ÷2 ÷4 ÷2 ÷16 ÷8 ÷4 CLK0 CLK1 REF_SEL 0 1 0 0 0 1 1 1 1 ÷2 FSEL0 FSEL1 FSEL2 QC 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 ÷8 ÷8 ÷6 ÷8 ÷4 ÷16 ÷8 ÷4 GND QA0:QA5 QA0 QA1 VDDO_A GND QA2 QB0:QB5 QA3 VDDO_A GND QA4 QA5 VDDO_A QC 36 35 34 33 32 31 30 29 28 27 26 25 37 24 38 23 39 22 40 21 41 20 48-Pin LQFP 42 7mm x 7mm x 1.4mm 19 43 18 body package 17 44 Y Package 45 16 46 15 Top View 14 47 48 13 1 2 3 4 5 6 7 8 9 10 11 12 GND QB0...