ICS8737-11 Description
The ICS8737-11 is a low skew, high performance Differential-to-3.3V LVPECL Clock Generator/ HiPerClockS™ Divider and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS8737-11 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels.
ICS8737-11 Key Features
- 2 divide by 1 differential 3.3V LVPECL outputs; 2 divide by 2 differential 3.3V LVPECL outputs
- Selectable CLK, nCLK or LVPECL clock inputs
- CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
- PCLK, nPCLK supports the following input types: LVPECL, CML, SSTL
- Maximum output frequency up to 650MHz
- Translates any single ended input signal (LVCMOS, LVTTL, GTL) to LVPECL levels with resistor bias on nCLK input
- Output skew: 60ps (maximum)
- Part-to-part skew: 200ps (maximum)
- Bank skew: Bank A
- 20ps (maximum), Bank B