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ICS8737-11 - CLOCK GENERATOR

General Description

The ICS8737-11 is a low skew, high performance Differential-to-3.3V LVPECL Clock Generator/ HiPerClockS™ Divider and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS.

The ICS8737-11 has two selectable clock inputs.

Key Features

  • 2 divide by 1 differential 3.3V LVPECL outputs; 2 divide by 2 differential 3.3V LVPECL outputs.
  • Selectable CLK, nCLK or LVPECL clock inputs.
  • CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL.
  • PCLK, nPCLK supports the following input types: LVPECL, CML, SSTL.
  • Maximum output frequency up to 650MHz.
  • Translates any single ended input signal (LVCMOS, LVTTL, GTL) to LVPECL levels with resistor bias.

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Datasheet Details

Part number ICS8737-11
Manufacturer Integrated Circuit Systems
File Size 127.62 KB
Description CLOCK GENERATOR
Datasheet download datasheet ICS8737-11 Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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Integrated Circuit Systems, Inc. LOW SKEW ÷1/÷2 DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR FEATURES • 2 divide by 1 differential 3.3V LVPECL outputs; 2 divide by 2 differential 3.3V LVPECL outputs • Selectable CLK, nCLK or LVPECL clock inputs • CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL • PCLK, nPCLK supports the following input types: LVPECL, CML, SSTL • Maximum output frequency up to 650MHz • Translates any single ended input signal (LVCMOS, LVTTL, GTL) to LVPECL levels with resistor bias on nCLK input • Output skew: 60ps (maximum) • Part-to-part skew: 200ps (maximum) • Bank skew: Bank A - 20ps (maximum), Bank B - 35ps (maximum) • Propagation delay: 1.7ns (maximum) • 3.