ICS9148-60 Datasheet PDF - Integrated Circuit Systems Frequency Generator & Integrated Buffers Specs

ICS9148-60 - Frequency Generator & Integrated Buffers

Datasheet Summary

Description

The ICS9148-60 is part of a reduced pin count two-chip clock solution for designs using an Intel BX style chipset.

Companion SDRAM buffers are ICS9179-11 and 12.

There are two PLLs, with the first PLL capable of spread spectrum operation.

Features

Generates system clocks for CPU, PCI, IOAPIC , 14.314 MHz, 48 and 24MHz. Supports single or dual processor systems Skew from CPU (earlier) to PCI clock 1 to 4ns Separate 2.5V and 3.3V supply pins 2.5V outputs: CPU, IOAPIC 3.3V outputs: PCI, REF No power supply sequence requirements 28 pin SOIC and SSOP Spread Spectrum operation optional for PLL1 CPU frequencies to 100MHz are supported. Pin Configuration Block Diagram 28 pin SOIC and SSOP Power Groups VDD = Supply for PLL.

Datasheet Details

Part number	ICS9148-60
Manufacturer	Integrated Circuit Systems
File Size	277.99 KB
Description	Frequency Generator & Integrated Buffers
Datasheet	ICS9148-60 Datasheet
Additional preview pages of the ICS9148-60 datasheet.

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Full PDF Text Transcription

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Integrated Circuit Systems, Inc. ICS9148-60 Pentium/ProTM System Clock Chip General Description The ICS9148-60 is part of a reduced pin count two-chip clock solution for designs using an Intel BX style chipset. Companion SDRAM buffers are ICS9179-11 and 12. There are two PLLs, with the first PLL capable of spread spectrum operation. Spread spectrum typically reduces system EMI by 8-10dB. The second PLL provides support for USB (48MHz) and 24MHz requirements. CPU frequencies up to 100MHz are supported. The I2C interface allows stop clock programming, frequency selection, and spread spectrum operation to be programmed. Clock outputs include two CPU (2.5V or 3.3V), seven PCI (3.3V), one REF (3.3V), one IOAPIC (2.5V or 3.3V), one 48MHz, and one selectable 48_24MHz.

Published: Feb 6, 2006 |