ICS9160-03 Datasheet | Integrated Circuit Systems

.. Integrated Circuit Systems, Inc. Preliminary Product Preview Frequency Generator and Integrated Buffer for Power PC® General Description The ICS9160-03 generates all clocks required for high speed RISC microprocessor systems based on the Power PC 603 and 604. Five different frequency multiplying factors are selectable and offer smooth frequency transitions. BCLK signals are synchronous to PCLK and operate at PCLK/2 for optimum synchronous PCI bus performance. The multiplying and ratio factors can be customed for specific applications. Both individual and group glitch-free stop and start ofthe clock signals are provided, as well as a power-down mode to mize power consumption. The individual stop and start is provided through a serial interface control. A global output enable pin simplifies production board testing, and a test mode is available to aid in system design and diagnostics. Features - - - - - - - - - Generates four processor and seven synchronous bus clocks plus graphic, floppy, keyboard and reference clocks Selectable 33.3/50/60/66.6/80 MHz PCLKs ±150ps maximum Power PC PLL in-band jitter All synchronous clocks skew matched to ±250ps Individual or group stop-clock control Power-down modes minimize standby current Custom configurations available 3.0V - 5.5 supply range 32-pin SOIC package Pin Configuration Data Shee . Block Diagram 28-Pin SOIC . 9160-03 Rev C 06/19/97P PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice. .. Preliminary Product Preview Pin Descriptions PIN NUMBER 2 3 1 4 5, 6, 7 8, 9, 11, 12 10, 17 13 PIN NAME X1 X2 VDDX GNDX FS(0:2) PCLK(0:3) VDDP GNDP TYPE IN OUT PWR IN OUT PWR DESCRIPTION XTAL or external reference frequency input. This input includes XTAL load capacitance and feedback bias for a...