ICS91857 Datasheet | Integrated Circuit Systems

.. Integrated Circuit Systems, Inc. Value SSTL_2 Clock Driver (60MHz - 220MHz) Remended Application: Zero delay board fan-out memory modules Product Description/Features : - Meets PC3200 specification for DDRI-400 support - Low skew, low jitter PLL clock driver - 1 to 10 differential clock distribution (SSTL_2) - Feedback pins for input to output synchronization - PD# for power management - Spread Spectrum tolerant inputs - Auto PD when input signal removed Switching Characteristics: - CYCLE - CYCLE jitter (>100MHz):<75ps - OUTPUT - OUTPUT skew: <100ps Pin Configuration GND CLKC0 CLKT0 VDD CLKT1 CLKC1 GND GND CLKC2 CLKT2 VDD VDD CLK_INT CLK_INC VDD AVDD AGND GND CLKC3 CLKT3 VDD CLKT4 CLKC4 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 GND CLKC5 CLKT5 VDD CLKT6 CLKC6 GND GND CLKC7 CLKT7 VDD PD# FB_INT FB_INC VDD FB_OUTC FB_OUTT GND CLKC8 CLKT8 VDD CLKT9 CLKC9 GND 48-Pin TSSOP 6.10 mm. Body, 0.50 mm. pitch TSSOP Functionality INPUTS AVDD PD# GND GND 2.5V (nom) 2.5V (nom) 2.5V (nom) 2.5V (nom) 2.5V (nom) H H L L H H X CLK_INT L H L H L H <20MHz)(1) OUTPUTS PLL State CLK_INC CLKT CLKC FB_OUTT FB_OUTC H L H L H L L H Z Z L H Z H L Z Z H L Z L H Z Z L H Z H L Z Z H L Z Bypassed/off Bypassed/off off off Block Diagram FB_OUTT FB_OUTC CLKT0 CLKC0 CLKT1 CLKC1 Control on on off PD# Logic CLKT2 CLKC2 CLKT3 CLKC3 CLKT4 CLKC4 FB_INT FB_INC CLK_INC...