ICS9248-99 Datasheet PDF - Integrated Circuit Systems Frequency Generator & Integrated Buffers Specs

ICS9248-99 - Frequency Generator & Integrated Buffers

Datasheet Summary

Description

The ICS9248-99 is the single chip clock solution for Desktop designs using 810/810/E style chipset.

It provides all necessary clock signals for such a system.

Spread spectrum may be enabled through I2C programming.

Features

2- CPUs @2.5V @ 150MHz (up to 200MHz. achievable through I2C).
9 - SDRAM @ 3.3V @ 150MHz (up to 200MHz. achievable through I2C).
8 - PCICLK @ 3.3V.
1 - IOAPIC @ 2.5V,.
2 - 3V66MHz @ 3.3V.
2- 48MHz, @ 3.3V fixed.
1- 24/48MHz, @ 3.3V.
1- REF @3.3V, 14.318MHz. Features:.
Up to 200.4MHz frequency support.
Support FS0-FS3 trapping status bit for I2C read back.
Support power management: Power down Mo.

Datasheet Details

Part number	ICS9248-99
Manufacturer	Integrated Circuit Systems
File Size	451.99 KB
Description	Frequency Generator & Integrated Buffers
Datasheet	ICS9248-99 Datasheet
Additional preview pages of the ICS9248-99 datasheet.

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Full PDF Text Transcription

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Integrated Circuit Systems, Inc. ICS9248-99 Preliminary Product Preview Frequency Generator & Integrated Buffers for Celeron & PII/III™ Recommended Application: 810/810E style chipset Output Features: • 2- CPUs @2.5V @ 150MHz (up to 200MHz. achievable through I2C) • 9 - SDRAM @ 3.3V @ 150MHz (up to 200MHz. achievable through I2C) • 8 - PCICLK @ 3.3V • 1 - IOAPIC @ 2.5V, • 2 - 3V66MHz @ 3.3V • 2- 48MHz, @ 3.3V fixed. • 1- 24/48MHz, @ 3.3V • 1- REF @3.3V, 14.318MHz. Features: • Up to 200.4MHz frequency support • Support FS0-FS3 trapping status bit for I2C read back. • Support power management: Power down Mode form I2C programming. • Spread spectrum for EMI control ( ± 0.25% center). • FS0, FS1, FS2, FS3 must have a internal 120K pull-Down to GND. • Uses external 14.

Published: Oct 7, 2005 |