ICS95V860 Description
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ICS95V860 Key Features
- Low skew, low jitter PLL clock driver
- 1 to 13 differential clock distribution (SSTL_2)
- Feedback pins for input to output synchronization
- PD# for power management
- Spread Spectrum-tolerant inputs
- Auto PD when input signal removed
- 0°C to 85°C operation Switching Characteristics
- CYCLE jitter (>100MHz):<75ps
- OUTPUT
- OUTPUT skew: <70ps