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ICSSSTVA16857 Datasheet Ddr 14-bit Registered Buffer

Manufacturer: Integrated Circuit Systems

Overview: Integrated Circuit Systems, Inc. ICSSSTVA16857 DDR 14-Bit Registered Buffer Remended Applications: • DDR Memory Modules • Provides plete DDR DIMM logic solution with ICS93V857 or ICS95V857 • SSTL_2 patible data.

General Description

The 14-bit ICSSSTVA16857 is a universal bus driver designed for 2.3V to 2.7V VDD operation and SSTL_2 I/O levels, except for the LVCMOS RESET# input.

Data flow from D to Q is controlled by the differential clock (CLK/CLK#) and a control signal (RESET#).

The positive edge of CLK is used to trigger the data flow and CLK# is used to maintain sufficient noise margins where as RESET#, an LVCMOS asynchronous signal, is intended for use at the time of power-up only.

Key Features

  • Exceeds "SSTVN16857" performance.
  • Differential clock signal.
  • Meets SSTL_2 signal data.
  • Supports SSTL_2 class I & II specifications.
  • Low-voltage operation - VDD = 2.3V to 2.7V.
  • 48 pin TSSOP package Pin Configuration Q1 Q2 GND VDDQ Q3 Q4 Q5 GND VDDQ Q6 Q7 VDDQ GND Q8 Q9 VDDQ GND Q10 Q11 Q12 VDDQ GND Q13 Q14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 D.

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